1. Field of the Disclosure
The present disclosure relates to processes of forming electronic devices, and more particularly, processes of forming the electronic devices that include forming a gate electrode layer and a patterned masking layer.
2. Description of the Related Art
The challenge of forming electronic devices continues to increase as more functionality is put into a smaller area. From a cross-sectional view, the aspect ratio of gate electrode structures continues to increase with successive generations of electronic devices. Taller, thinner structures are more fragile and therefore more likely to be damaged during subsequent processing than structures with a lower aspect ratio. Such structures are particularly problematic with respect to cleaning, stripping, and layer removal processes where additional thinning of the structures occurs.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention. The use of the same reference symbols in different drawings indicates similar or identical items.